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Adithiya_R's avatar
Adithiya_R
Icon for New Contributor rankNew Contributor
1 year ago
Solved

Intel P-tile Avalon ST BAR0 addr_offset

Hi Everyone, I am using Ptile-pcie ip in endpoint mode, Gen4 1x8 256 bit configuration and Quartus 23.4 I have an issue regarding bar0_write with a different offset. I tried the following tlp [Da...
Pcie
  • VenT_Altera's avatar
    VenT_Altera
    1 year ago

    Hi Adithiya_R,

    Thanks for sharing your observation.


    This is an expected behavior. The TLP header and data are dword aligned. There is no workaround to change the address alignment that I am aware of.


    If you use the BAM and BAS modes on P-Tile, the AVMM address is aligned to the natural width of the data. For example, if the data width is 64B, the addresses must align to 64B.


    Thanks.

    Best Regards,

    Ven


VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi Adithiya_R,

Thank you for confirming the answer provided.


Could you please create a new forum post about the new inquiries on the clock and timing analysis?

We prefer to have separate issues or inquiries filed for each distinct support issue to ensure better tracking and resolution.


Since the initial inquiries on the P-Tile AVST BAR have been addressed, I will transition this forum to community support.


Thank you for your understanding.


Thanks.

Best Regards,

Ven