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DLync7's avatar
DLync7
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5 years ago

Intel FPGA IP Evaluation Mode Issue

Hi, I'm trying to evaluate various IP cores (NCO, FFT, TSE, NIOS II/f). However, I'm only ever able to get simulation only mode from them. The error message when doing analysis and synthesis is:...
DLync7's avatar
DLync7
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5 years ago

Hi,

When I generate an IP core to evaluate (FFT for example), I use these settings

 All I do after that is add the .ip file to the project. Once it is added I get this message:

I have gone through every setting tab and made sure all the settings are the same as a blank project (signaltap off, logic analyzer off, simulation tool none). I have also tried deleting any qdb folders, the tmp-clearbox folder, the .qdf file and any .bak files related to settings.

If I don't have that fft ip file added I can generate regular .sof files fine and I have other IP that I have already purchased included in the project.

KMour's avatar
KMour
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5 years ago

Hi DLync7,

Did you figure out a way to get the FFT IP working in evaluation mode? I've been dealing with exactly the same problem (Cyclone 10 GX device in Quartus Prime Pro 19.4).

Thanks,

Kyle

  • DLync7's avatar
    DLync7
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    5 years ago

    Hi Kyle,

    No I was not able to fix the issue.

    What I have noticed is that I had no trouble getting evaluation mode to work on a DE1-SOC (Cyclone V, Quartus Lite V20.1), however when using a DE10-Nano (Cyclone V, Quartus Lite 20.1) I had the same issues.

    I can't think of any reason why two different Cyclone V devices in Quartus Lite would exhibit different behaviour in regards to IP cores.

    I have noticed other people have had this issue in the forums but have not seen a solution that fixes the underlying problem.

    Thanks

    -David

    • KMour's avatar
      KMour
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      5 years ago

      Hi David,

      Thanks for the follow-up. That's a bizarre situation. I would have guessed that it was related to the Quartus install. I'll let you know if I'm able to get it working.

      Best,

      Kyle

      • DLync7's avatar
        DLync7
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        5 years ago

        Hi,

        As an update I have not been able to fix the issue.

        However I did find something that may help.

        I had a Quartus Lite project that was using an NCO in evaluation mode successfully. It was a very small project, merely outputting a sin and cos wave on a DAC.

        Once verified that it was working, I added a lot of logic to the project (>50% LE usage on the Cyclone V FPGA) and then it changed back to simulation mode only for the IP cores.

        I assume this is a bug at this point as I cant see any reason why adding logic that has nothing to do with licensing would change the IP core evaluate mode.