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jsondergaard
New Contributor
New ContributorIntel FPGA Avalon I2C (Host) Core
Does anyone have an example or tutorial on how to use this core on an SoC? I have had success with the Cyclone V using other cores and writing to their registers from the HPS via the Avalon mm to suc...
The register addresses in the datasheet actually need to be multiplied by four. Everything is working just fine now.
jsondergaardNew Contributor
New ContributorEberlazare,
I appreciate the suggestion. This appears to be a different core than the "Intel FPGA Avalon I2C (Host) Core." It is also meant for a MAX 10 dev kit, so the hardware isn't quite the same. I probably should've mentioned that I am using the DE10-Nano from Terasic. With that said, the general Qsys connections I have on my end are relatively the same.
Thank you,
Jordan
jsondergaardNew Contributor
New ContributorThe register addresses in the datasheet actually need to be multiplied by four. Everything is working just fine now.
