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User1582192733150209's avatar
User1582192733150209
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Intel FFT IP core timing issue

Hello Sir/Madam, I am simulating the intel FFT IP core, and seems FFT output has some timing issue . Quartus prime pro 17.1 Modelsim-intel starter 10.5c Windows 10 pro Arria10gx FFT con...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Yes, I can see the same problem in v20.1, and will feedback to the Intel FPGA FFT IP engineering team.


For the moment, you may increase the inter-packet gap number to work around the issue. For example, you can change the IPG_number to 256 in your testbench.


Regards -SK


User1582192733150209's avatar
User1582192733150209
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hi SK,

I have verified that by increasing the IPG of repeat packet input, the outputting relevant signals can go back to correct timing. For that purpose , the minimum IPG is 256 for this case, any other number less than 256 will have same glitch and timing issue.

this workaround can solve the timing issue, the cost is FFT processing bandwidth reduced .

hope can have some vendor patch to solve this.

thanks

Jim