Integrating Altera's FFT IP Core into Nios System

Hi all

I am new here and i have a problem with integrating Altera's FFT IP Core into a NIOS II System. I am using Quartus 7.1 and also Megacore IP 7.1.

I already have made a simple NIOS System with CPU, on-chip memory, uart jtag and timer. Now i want to integrate the FFT IP Core.

My first problem is that i cannot make a correct component of the FFT in SOPC Builder. I have already made a version of the FFT Core through the use of the MegaWizard Plug-in Manager. So far so good. Now when i specifiy to make a new component in SOPC Builder in the component editer and choose the verilog file of the FFT it shows me all the signal (sink and source signals of the Avalon ST interface and also clk, reset). Now all the signals get assigned to global signals as interface. And the interface itself is empty. When i add a new interface i cannot choose to make a Avalon ST interface. Only Slave, Master, Custom Intstruction and Tristate. But no matter what i choose it always gets deleted after i finish the component. By clicking on add i get a empty list for the signals and the component won't get added to my NIOS system. Can anybody tell me how to make a component which is using the Avalon ST interface ? Every tutorial i found so far is about dealing with components using the Avalon MM interface.

The second problem is how to connect the FFT to the NIOS CPU. The NIOS CPU is of course using the Avalon MM interface so i have to make a "conversion" to the Avalon ST Interface. I found that you can use FIFO's and specifiy each input and output to be either MM or ST. So that should work. But i am wondering if there is a better way to do this ? For example using those Avalon ST Sink and Source components from the Debug and Performance Peripherals. Sadly i haven't found any documentation about those two components and what they actually really are doing.

Thanks for reading and any help.

Flo