Integrating a Avalon FIFO IP to the PCIe DMA transfer example design for Arria 10 GX

HI Thank you for addressing my problem. Unfortunately that did not help me much.

I have some questions too. I already have the Address section -> Use automatically-determined address width enabled for Avalon Pipeline Bridge IP. Changing Address unit of WORDS gives some error "Port mismatch could not be auto resolved. Double click for manual resolution". We merged the interface and that resolved the errors.

Also, you suggested me to set the Base address of the Avalon FIFO Memory IP to 0x1_0000_0000 or higher to avoid the address overlapping. But I really would like to know you suggested me to do System->Assign Base Address (which I did and still problem persists. Screenshot attached 3.PNG ) or putting it manually. We put it manually and it says it's outside the master's address range.

Also, I noticed that the design you re-created (from the screenshot posted above) does not have some IP components like Avalon-MM Clock Crossing Bridge Intel FPGA IP (which is an IP in the QSYS file Demonstartions/PCIe_DDR4/ep_g3x8_avmm256_integrated.qsys while opening in System Builder).

I would like to explain the problem in bit more detail. I was trying to integrate a Avalon FIFO IP with the PCIe DMA Transfer Example design for Windows (Provided in DE5a-Net CD/Demonstrations/PCIe_DDR4/) mentioned in the Chapter-7 of the attached manual (DE5a-Net Arria 10 FPGA) attached as DE5a-Net_User_Manual.pdf. My objective is to stream data from QSFP+ to DDR4 memory, and then do a DMA transfer to a Computer through PCIe. I would also like to know if you could mention anything I have to be cautious in integrating an IP with a System Builder design.

I am explaining the step by step procedure I did

1. Opened th .qsys file of thePCIe DMA transfer example design (provided in the CD Demonstartions/PCIe_DDR4/ep_g3x8_avmm256_integrated.qsys) in System Builder.

2. Added Avalon FIFO IP with the example design. clk_in and reset_in are connected to global clock (Screenshot 1.PNG) --Can see message to connect fifo_15_in and fifo_15_out or export them.

3. Exported fifo_15_in port to connect tho QSFP+ later. You can see a warning message regarding the clock in screenshot 2.PNG (Could you mention how to get rid of this warning?)

4. Connected fifo_15_out with Avalon MM Pipeline bridge Intel FPGA IP's (corresponding to two DDR4 memory) . You can see the error messages regarding the memory overlap in screenshot 3.PNG -

5. Did System->Assign Base Address in System Builder and that did not resolve the issue. Then we tried putting it manually (the value you suggested `0x1_0000_0000`) and it says it's outside the master's address range.

6. Gets an additional error while changing Address unit from SYMBOLS to WORDS: "Port mismatch could not be auto resolved. Double click for manual resolution". Screenshot 4.PNG (We merged the interface and that resolved the errors)

Please let me know if you need any clarification. Any suggestion regarding my procedure to integrate IP with example design is also welcome.