travisa
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Re: Creating a new API for an FPGA design with Data Generator IP
Thank you very much for your reply. Actually my problem is bit different I assume. I want to use the Data Generator IP to generate data and send that data to the DDR memory. Then do a PCIe DMA transfer of the data to a host windows computer (Windows OS 10). For sending data from Data Generator IP to the DDR4 and doing DMA transfer from the DDR4 to the memory of host computer, I am planning to use the PCIe DMA transfer example (given in chapter 7 of attached document). But to generate data in the IP, I assume we needed an API in the host computer? (the host computer is connected to FPGA through PCIe as well as USB). https://www.intel.com/content/www/us/en/docs/programmable/683609/21-3/data-pattern-generator-ip-api.html Talks about the API’s for this. But I would like to know how to get a “.DLL” file and driver file for this. Also can I use the API for PCIe DMA transfer and API for Data Generator IP simultaneously from the host computer?2.4KViews0likes0CommentsCreating a new API for an FPGA design with Data Generator IP
Hi, I am working on a hardware design in my DE5A-NET-DDR4 fpga using the Quartus Prime Pro tool. In the system builder, I have the Intel Data Generator IP. I have to have an API in my host computer (that connected to the FPGA through both PCIe and USB ports). It would be great if I get a help to understand how create an API from scratch and to know how to get the .DLL file for this example. I can find an API and the driver file for the PCIe DMA Transfer example. Can I use the same .DLL (driver file) for communicating with Inter Data Generator IP design and the API?2.4KViews0likes4CommentsRe: Integrating a Avalon FIFO IP to the PCIe DMA transfer example design for Arria 10 GX
Hi Adzim, Thank you very much for explaining things very well. I have a couple of quick questions too. What is the real cause of the error "Port mismatch could not be auto resolved. Double click for manual resolution"? I it just merge option by double clicking the error? (Attached screenshot 7.PNG gets after double clicking the port mismatch message ). What is the recommended solution for this and what are the things we must consider in selecting between accept default or accept merge options in the screenshot. Also, in the last e-mail, you mentioned "you should take care the data that will be connected to FIFO". Could you please elaborate it little bit? What are the specs. of data that I should take care? Thanks again!5.4KViews0likes0CommentsRe: Integrating a Avalon FIFO IP to the PCIe DMA transfer example design for Arria 10 GX
Hi, Thank you very much for recreating my problem and sending me the file. I tried compiling it and succeeded. I would like to ask some questions regarding this. So I am explaining the steps I followed to run the .qsys file and attaching relevant screenshots. 1. I worked in my DE5a-Net "CD/Demonstrations/PCIe_DDR4/" folder and opened PCIe_DDR4.qpf Quartus Project file opened the ep_g3x8_avmm256_integrated.qsys in the System Builder. 2. Changed Address unit from SYMBOLS to WORDS for Avalon MM Pipeline Bridge IP and Avalon MM Clock-crossing Bridge IP. This throws an error as shown in CaptureA1.PNG. Resolved the port mismatch manually to resolve the errors. I have a question regarding this step. What is the real cause of the error "Port mismatch could not be auto resolved. Double click for manual resolution" and what is the recommended solution for this. I it just merge option by double clicking the error? Also, is there any reason other than improving the IP timing for changing Address unit from SYMBOLS to WORDS 3. I have added the Avalon MM FIFO IP and Clock Bridge IP to the design. (I really would like to know is there any specific reason you used clock bridge IP to clock FIFO IP, instead of the clock from Clock IP or Clock from Avalon-MM DMA Hard IP?) 4. Connecting the out slave of FIFO IP with the masters from m0 from Avalon MM Pipeline Bridge IP. This gives the memory overlap issue. Would you please remind me why we should change the address specifically to 0x1_0000_0000 or higher? By changing address to what you suggested removes error messages. Then ran the Generate HDL (as seen in CaptureA9.PNG (do we want to worry about the warning messages as seen in screenshot?) and then successfully compiled the project. I am planning to make a custom IP that create random bits that should stream through FIFO to DMA and which in turn DMA transferred to a PC through PCIe. I there any thing we should be cautious in creating a custom IP that creates bits and feeds to FIFO?. Thank you very much.5.5KViews0likes0CommentsAdding an Avalon FIFO IP with PCIeDMA Transfer Example design (Provided in CD) for Arria 10 GX FPGA
Hi, I am trying to stream in data from an external source (through QSFP+) to the DDR4 memory and then do a DMA transfer the data to a Computer through PCIe. For that I would like to use a FIFO to push data (that comes from QSFP+) into the DDR4 elements. My plan is to integrate the Avalon FIFO Memory Intel FPGA IP with the PCIe DMA transfer example design for Windows (Provided in DE5a-Net CD/Demonstrations/PCIe_DDR4/) mention in the Chapter-7 (section 7.6 from page number 130) of the attached manual (DE5a-Net Arria 10 FPGA) DE5a-Net_User_Manual.pdf. Any suggestion or documentation for an additional IP with an example design is most welcome. PS: I am working in DE5a-Net-DDR4 Arria 10 GX (10 AX115N2F45E1SG) and use Quartus Prime Pro version 18.17.2KViews0likes1CommentRe: Integrating a Avalon FIFO IP to the PCIe DMA transfer example design for Arria 10 GX
HI Thank you for addressing my problem. Unfortunately that did not help me much. I have some questions too. I already have the Address section -> Use automatically-determined address width enabled for Avalon Pipeline Bridge IP. Changing Address unit of WORDS gives some error "Port mismatch could not be auto resolved. Double click for manual resolution". We merged the interface and that resolved the errors. Also, you suggested me to set the Base address of the Avalon FIFO Memory IP to 0x1_0000_0000 or higher to avoid the address overlapping. But I really would like to know you suggested me to do System->Assign Base Address (which I did and still problem persists. Screenshot attached 3.PNG ) or putting it manually. We put it manually and it says it's outside the master's address range. Also, I noticed that the design you re-created (from the screenshot posted above) does not have some IP components like Avalon-MM Clock Crossing Bridge Intel FPGA IP (which is an IP in the QSYS file Demonstartions/PCIe_DDR4/ep_g3x8_avmm256_integrated.qsys while opening in System Builder). I would like to explain the problem in bit more detail. I was trying to integrate a Avalon FIFO IP with the PCIe DMA Transfer Example design for Windows (Provided in DE5a-Net CD/Demonstrations/PCIe_DDR4/) mentioned in the Chapter-7 of the attached manual (DE5a-Net Arria 10 FPGA) attached as DE5a-Net_User_Manual.pdf. My objective is to stream data from QSFP+ to DDR4 memory, and then do a DMA transfer to a Computer through PCIe. I would also like to know if you could mention anything I have to be cautious in integrating an IP with a System Builder design. I am explaining the step by step procedure I did 1. Opened th .qsys file of thePCIe DMA transfer example design (provided in the CD Demonstartions/PCIe_DDR4/ep_g3x8_avmm256_integrated.qsys) in System Builder. 2. Added Avalon FIFO IP with the example design. clk_in and reset_in are connected to global clock (Screenshot 1.PNG) --Can see message to connect fifo_15_in and fifo_15_out or export them. 3. Exported fifo_15_in port to connect tho QSFP+ later. You can see a warning message regarding the clock in screenshot 2.PNG (Could you mention how to get rid of this warning?) 4. Connected fifo_15_out with Avalon MM Pipeline bridge Intel FPGA IP's (corresponding to two DDR4 memory) . You can see the error messages regarding the memory overlap in screenshot 3.PNG - 5. Did System->Assign Base Address in System Builder and that did not resolve the issue. Then we tried putting it manually (the value you suggested `0x1_0000_0000`) and it says it's outside the master's address range. 6. Gets an additional error while changing Address unit from SYMBOLS to WORDS: "Port mismatch could not be auto resolved. Double click for manual resolution". Screenshot 4.PNG (We merged the interface and that resolved the errors) Please let me know if you need any clarification. Any suggestion regarding my procedure to integrate IP with example design is also welcome.5.5KViews0likes1CommentIntegrating a Avalon FIFO IP to the PCIe DMA transfer example design for Arria 10 GX
Hi, I am trying to stream in data from an external source (through QSFP+) to the DDR4 memory and then do a DMA transfer the data to a Computer through PCIe. For that I would like to use a FIFO to push data (that comes from QSFP+) into the DDR4 elements. My plan is to integrate the Avalon FIFO Memory Intel FPGA IP with the PCIe DMA transfer example design mention in the Chapter-7 of the attached manual (DE5a-Net Arria 10 FPGA). When try to add the FIFO IP to the example design in the System Builder, (here two "m0" master ports from Avalon MM Pipeline bridge Intel FPGA IP's (corresponding to two DDR4 memory) has to connect to the "out" slave port of the FIFO) I get a memory overlap error (Screenshot CaptureL1.png) when I did base address assignment to the "out" port. (Screenshot attached CaptureL2.png). Any suggestion or comment regarding the way I try to do the integration of FIFO IP with the example design is most welcome. Also it would be great if someone could help me out of the slave address overlapping issue (generally how to allocate memory for a slave, when connecting to a master that already have a slave with an allocated memory) mentioned in the above paragraph. Feel free to ask any question if you need any further clarification of the problem. PS: I am working in DE5a-Net-DDR4 Arria 10 GX (10 AX115N2F45E1SG) and use Quartus Prime Pro version 18.15.6KViews0likes9CommentsRe: PCIe DMA transfer design code Compilation error.
Hi, The expanded error massage you asked is attached (Quartus_Compilation_Error.png). Also, please see the underlined lines in the two fotos of verilog code where I have made a change (substitution.png and definition.png). Instead of initializing the "pcie_a10_hip_0_hip_pipe_sim_pipe_rate" to 1'b0 (please see the attached file DE5a_NET_Verilog_Error.png with error message, "Verilog HDL error at DE5A_NET.v(389): constant is not allowed"), I initialized it with a variable "entho" which is defined as wire[1:0]. With this hack, the project compiled without any error. Not sure that is what I am suppose to do to as a permanent solution. Do you have any suggestion regarding this?11KViews0likes0CommentsRe: PCIe DMA transfer design code Compilation error.
Hi, Yes we tried compilation of the project (after IP up-gradation) with Quartus Prime Pro v18.0 as well as 21.4, and unfortunately getting same error. Also when I tried to compile the /Demonstrations/PCIe_Fundamental/DE5A_NET.qpf, gets same error (screenshot attached) as gotten while compiling /Demonstrations/PCIe_DDR4/DE5A_NET.qpf. As I am beginner in Verilog also, could you please suggest the change I have to do in bit more detail. Thank you.12KViews0likes0CommentsRe: PCIe DMA transfer design code Compilation error.
Hello, We retrograded our version of Quartus Prime Pro to 18.1. We also redownloaded the System CD provided by Terasic. /*link may require a Terasic account*/ http://download.terasic.com/downloads/cd-rom/de5a-net-ddr4/ We opened up the ../Demonstrations/PCIe_DDR4/DE5A_NET.qpf in Quartus Prime Pro 18.1.0.222. From there we opened up ep_g3x8_avmm256_integrated.qsys in Platform Designer as part of the Auto Upgrade Process. I've attached the PCIe_DDR4.7z for our exact project after upgrades. Generating TestBench worked fine with few warnings (see Warnings image). Generating HDL worked fine too, again with a couple warnings (see two attached images). However Compilation of the project quickly encounters errors (see the 2 Error images). We seem to be narrowing down the issue. We had received this exact same Compilation error in Quartus Prime Pro 21.1. Forgive me for not understanding Verilog as well as I should. But I am still working to resolve "Verilog HDL error at DE5A_NET.v(389): constant is not allowed", successfully compile our project, and program our Arria 10 GX 10AX115N2F45E1SG.12KViews0likes0Comments