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travisa's avatar
travisa
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3 years ago

Creating a new API for an FPGA design with Data Generator IP

Hi,

I am working on a hardware design in my DE5A-NET-DDR4 fpga using the Quartus Prime Pro tool. In the system builder, I have the Intel Data Generator IP. I have to have an API in my host computer (that connected to the FPGA through both PCIe and USB ports). It would be great if I get a help to understand how create an API from scratch and to know how to get the .DLL file for this example. I can find an API and the driver file for the PCIe DMA Transfer example. Can I use the same .DLL (driver file) for communicating with Inter Data Generator IP design and the API?

4 Replies

  • Jeet14's avatar
    Jeet14
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    3 years ago

    Hi,


    We don’t have any driver for Data generator IP with NIOS or HPS.

    If I assume you want to use Data generator IP to generate the data at FPGA side and sending data to HPS/NIOS peripherals then you can use in between the Data generator-->DMA-->HPS/NIOS DDR memory.

    For this you can make use of the DMA driver API's with HPS/NIOS.


    If you are looking to write own custom driver API, then you can refer the guideline given for Developing Programs Using the Hardware Abstraction Layer & Developing Device Drivers for the Hardware Abstraction Layer.

    Reference is given on https://www.intel.com/content/www/us/en/docs/programmable/683282/current/developing-device-drivers-for-the-hardware-60162.html


    Regards

    Tiwari


  • travisa's avatar
    travisa
    Icon for New Contributor rankNew Contributor
    3 years ago

    Thank you very much for your reply. Actually my problem is bit different I assume. I want to use the Data Generator IP to generate data and send that data to the DDR memory. Then do a PCIe DMA transfer of the data to a host windows computer (Windows OS 10). For sending data from Data Generator IP to the DDR4 and doing DMA transfer from the DDR4 to the memory of host computer, I am planning to use the PCIe DMA transfer example (given in chapter 7 of attached document). But to generate data in the IP, I assume we needed an API in the host computer? (the host computer is connected to FPGA through PCIe as well as USB).

    https://www.intel.com/content/www/us/en/docs/programmable/683609/21-3/data-pattern-generator-ip-api.html

    Talks about the API’s for this. But I would like to know how to get a “.DLL” file and driver file for this.

    Also can I use the API for PCIe DMA transfer and API for Data Generator IP simultaneously from the host computer?

  • Jeet14's avatar
    Jeet14
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,


    Its taking long time as this is not generic query on .DLL files.

    I am checking internally if this is possible to get the .DLL files.

    Will update you ASAP.


    Regards

    Jeetesh


  • Jeet14's avatar
    Jeet14
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,


    I further checked on the .DLL files.

    Unfortunately, there is no .DLL for the IP block you have mentioned.

    You may need to use the JTAG to Avalon Master bridge and system console to perform this action.


    Let me know if you have any other question on this case.


    Regards

    Jeetesh