Instantiating 2 JESD204B cores to interface with DACs. Fitter place errors on 8 TX : "Could not find path between source HSSI PMA Aux. block and the Transmitter channel."

Please check my replies to your questions in bold:

Do I need to use a Tx PLL for the JESD core and another for the SFP+ core? If both are running at different rates, then yes you need to use 2 Tx PLL.

And, what are the external connections to the Tx PLL? Does my reference clock go to REFCLK1R or the Tx PLL (GXB_TX_R7 in my example below)?​ Your reference clock only goes to the REFCLK pin as described in the Arria 10 Transceiver User Guide and Pin Connection Guideline. The reference clock will be routed from the pin to the Tx PLL internally.

Regards,

Nathan