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Zarquin's avatar
Zarquin
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Incorrect values from TX-Fifo in Avalon PCIe Example

The endpoint TX-Fifo from the Avalon-ST Chaining DMA PCIe example outputs an incorrect tx_st_eop signal. During a signal tap II analysis of the Chaining DMA example, I noticed that the tx_st_eop r...
Pcie
  • FvM's avatar
    FvM
    3 years ago

    Hi,
    still think that it's a misinterpretation of tx_st interface data. st_data and st_sop and st_eop are only valid while st_valid is active. I know that in typical Avalon ST examples, sop and eop are reset together with valid, but as far as I understand, it's not required by the specification. See this explanation of valid signal:


    Asserted by the source to qualify all other source to sink signals. On ready cycles where valid is asserted, the data bus and other source to sink signals are sampled by the sink, and on other cycles are ignored.

    Regards,
    Frank

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi

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