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Zarquin's avatar
Zarquin
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Incorrect values from TX-Fifo in Avalon PCIe Example

The endpoint TX-Fifo from the Avalon-ST Chaining DMA PCIe example outputs an incorrect tx_st_eop signal. During a signal tap II analysis of the Chaining DMA example, I noticed that the tx_st_eop r...
Pcie
  • FvM's avatar
    FvM
    3 years ago

    Hi,
    still think that it's a misinterpretation of tx_st interface data. st_data and st_sop and st_eop are only valid while st_valid is active. I know that in typical Avalon ST examples, sop and eop are reset together with valid, but as far as I understand, it's not required by the specification. See this explanation of valid signal:


    Asserted by the source to qualify all other source to sink signals. On ready cycles where valid is asserted, the data bus and other source to sink signals are sampled by the sink, and on other cycles are ignored.

    Regards,
    Frank

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


According to your case about tx_st_ready not triggering.

First, Tx_st_ready deasserted indicates that the Transaction Layer is not ready to accept data for transmission.

In this case PCIe core will deasserts st_ready to throttle the data stream.

There are many possible causes for deassertion of tx_st_ready, there were documented in Chapter 18 (Table 18-2) of Cyclone V PCIe User Guide:

See section 'Debugging Link Failure in L0 Due To Deassertion of tx_st_ready'

https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_c5_pcie_avst.pdf

- Avalon-ST signaling violates Avalon-ST protocol

- Incorrect payload size

- Flow control credit overflows

- Malformed TLP is transmitted

- Insufficient Posted credits released by Root Port

- Missing completion packets or dropped packets

Kindly review the above possibilities, such as all previous transactions had started with a proper SOP and terminated by an EOP.


Regards,

Wincent_Intel