Forum Discussion
Occasional ContributorIncorrect values from TX-Fifo in Avalon PCIe Example
Hi,
still think that it's a misinterpretation of tx_st interface data. st_data and st_sop and st_eop are only valid while st_valid is active. I know that in typical Avalon ST examples, sop and eop are reset together with valid, but as far as I understand, it's not required by the specification. See this explanation of valid signal:
Asserted by the source to qualify all other source to sink signals. On ready cycles where valid is asserted, the data bus and other source to sink signals are sampled by the sink, and on other cycles are ignored.Regards,
Frank
Super ContributorHi,
do you observe an actual misbehavior of the PCIe IP? The shown screenshot shows expectabable FIFO behavior, the last read result is kept til next read. If there's an issue at all, it's not the FIFOs responsibility.
Expected processing on the sink side:
- perform a read if empty==0
- evaluate the fifo output once in next clock cycle
Occasional ContributorHello FvM,
well, the problem is that the TX-Tranfers don't look correct as I mentioned above:
I noticed that the tx_st_eop remains high after one clock cycle instead of going low.
It looks like this:
Wrong tx_st_eop Signal
and further like this
More wrong tx_st_eof signals
