In the Low Latency 100G Ethernet Intel®Stratix® 10 FPGA IP Core, can one of the two ATX PLLs be used as a clock buffer?

Hi @[DeshiL_Intel]​ ,

Thanks a lot for looking into this. From this discussion, I would summarize:

It is better to use one ATX PLL as a clock buffer while the other one being the main ATX PLL.

Based on our discussion in https://forums.intel.com/s/question/0D50P00004ZiXY6SAN/does-an-atx-pll-configured-as-a-clock-buffer-need-a-reference-clock-of-its-own-or-can-the-pllrefclk0-port-be-tied-to-ground, it would also be okay to tie the reference clock input of the ATX PLL being used as a clock buffer because it is merely being used as a buffer and would not require a clock unless we need to reconfigure it.

Please correct me if I am wrong.

Even though it is clearly mentioned in the H-Tile Hard IP for Ethernet User guide that one of the ATX PLLs is being used as a buffer, the 100G Low Latency User guide does not specify that it is okay to use it other than Figure 4.

Thanks,

Naved