In the Low Latency 100G Ethernet Intel®Stratix® 10 FPGA IP Core, can one of the two ATX PLLs be used as a clock buffer?

Hi Naved,

I look deeper into the example design.

Now I understand your concern and also see where is the problem.

Basically Intel FPGA offer both soft and hard Ethernet 100G IP and so happen their example design implementation is difference

For H-tile Hard IP for Ethernet :

• The example design used 2 ATX PLL in cascading mode (as clk buffer)

For low latency 100G soft Ethernet IP :

• The example design used 2 ATX PLL as 2 separate PLL (NOT as clk buffer, just used as PLL)

Attached is the screenshot showing you the example design connection difference

Meaning low latency 100G soft Ethernet IP user guide doc - figure 4 diagram and explanation is wrong.

• I will take the action to feedback to our Intel doc team accordingly

FYI... Intel does has separate 100G soft Ethernet IP example design doc that you can refer to as well

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-s10-ll-100gbe.pdf

Finally back to your original concern, regardless which PLL mode is being used, example design always recommend to connect both PLL refclk pins to ONE same FPGA external refclk pin.

Thanks.

Regards,

dlim