New Contributor
Regular ContributorHi,
I can see that you have asked similar enquiry on another forum case
and I have explained the ATX PLL clock buffer refclk connection guideline to you
Does it help or you are still confused ?
Thanks.
Regards,
dlim
New ContributorHi @DeshiL_Intel ,
My concern in this post is that I am using the 100G Low Latency Ethernet IP and in it's userguide, except for this diagram shown in the above figure (Figure 4), is it mentioned everywhere throughout the userguide that the input reference clock should come in through a DEDICATED REF CLOCK pin. For jitter purposes, I want to know whether the input reference clock should come in though a dedicated reference clock for both the instantiated ATX PLLs or can one these be used as a buffer as in Figure 4 shown. If we are able to use just one Reference clock input, it might save us some board routing while I want to make sure whether it is recommended or not for 100G Low Latency Ethernet IP for Stratix 10.
Pointing you to the userguide where it mentions that two "Transmit" ATX PLL should be used with reference clock input through a dedicated reference clock pin with +-100ppm accuracy:
Please note that I have underlined "transmit". I hope this is an understandable concern.
New ContributorActually now that I see this, the documentation just meant to use the full form of the acronym ATX where I have underlined it. Nonetheless, I still wanted to make sure whether it can be used as a buffer for this IP.
