Implementing MSI-X in Agilex 7 Rtile MCDAM PCIe based design

I am using Agilex 7 - AGIB027R29A1E2VC FPGA. On Rtile I am using Multi Channel DMA FPGA IP for PCI
Express - Data Movers Only. https://www.intel.com/content/www/us/en/docs/programmable/683821/25-1-1/data-mover-only.html  My design currently performs H2D and D2H DMAs as I need to.

Now I want to send MSI-X interrupt after certain DMA completion and thats where I need help.  Specifically "MSI-X Enable" and "MSI-X function mask" related functionality. Other Parts related to implementing MSI-X is clear to me.  "MSI-X Enable" and "MSI-X function mask" both can be written by host side driver and the interrupt controller inside PCIe ep device is supposed behave accordingly. 

Currently I am struggling to figure out how can I get a copy of CFG writes to MSI-X capability structure  when CFG WRs are targeting  "MSI-X Enable" and "MSI-X function mask"?  If I get a copy of such CFG writes than my application layer logic can keep track of latest value written and update MSI-X behavior as intended.

https://www.intel.com/content/www/us/en/docs/programmable/683501/25-1-1/msi-x.html mentions that "The R-Tile IP for PCIe provides a Configuration Intercept Interface. User soft logic can monitor this interface to get MSI-X Enable and MSI-X function mask related information."

https://www.intel.com/content/www/us/en/docs/programmable/683501/25-1-1/configuration-intercept-interface.html mentions that "The Configuration Intercept Interface (CII) allows the application logic to detect the occurrence of a Configuration (CFG) request on the link and to modify its behavior."

is there any example on how CII interface can be used to monitor MSI-X capability structure accesses? 

https://community.intel.com/t5/FPGA-Wiki/Implementing-MSI-X-for-PCI-Express-in-Altera-FPGA-Devices/ta-p/735678 this link appears to be broken 

furthermore, table 71 on https://www.intel.com/content/www/us/en/docs/programmable/683501/25-1-1/configuration-intercept-interface.html provides cii interface signal list and its details - after reviewing them I have following questions. 

1. pX_cii_wr_o    Output    Indicates that cii_dout_p0/1 is valid. This signal is asserted only for a configuration write request.
   • there is no mention of "pX_cii_rd_o" signal,   can pX_cii_wr_o signal be used to determine read request? if this signal is at logic 0 , does it mean that this is CFG read request?
2. pX_cii_addr_o[9:0]    Output    The double-word register address in the received TLP header on the CII. 
   • is this the address associated with CFW write? how do i know Config space offset at which MSI-X capability is located? So I can compare pX_cii_addr_o along with pX_cii_hdr_first_be_o to check if the CFG access to targeting "MSI-X Enable" or"MSI-X function mask" or not.
3. how do I use CII interface so it ignores all offsets other than MSI-X capability structure related