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Altera_Forum
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17 years ago

Implementaion of Megacore generated DDR2 SDRAM controller

Hi There I have a StratixII GX board and I need to prove our DDR2 core on this board. Is it possible to port our core to altmemphy and try implementation and generating bit file to prove on boa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

The controller is the one who issued the read and is responsible for knowing when the read data from the data path is valid.

Jake