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Honored Contributor
Honored ContributorImplementaion of Megacore generated DDR2 SDRAM controller
Hi There I have a StratixII GX board and I need to prove our DDR2 core on this board. Is it possible to port our core to altmemphy and try implementation and generating bit file to prove on boa...
Altera_ForumHonored Contributor
Honored ContributorDDR and DDR2 SDRAM Controller's cotrol logic is encrypted. I believe I can replace it with our core and try out. But the problem here is local_rdata_valid signal is coming out of control logic. Since the datapath does the read operation, hence datapath should give the associated rdata_valid signal with the control_rdata.
Please reply if anybody there has got some idea
