Forum Discussion
BoonT_Intel
Frequent Contributor
7 years agoHi George,
Thanks for the details. Your finding is correct.
When you turn off abstract PHY, the simulation expect a memory component that allow the interface to perform read/write.
The bus functional model that generate using Platform designer (Qsys) will not work like a memory model (eg read/write from specific address). Thus, you have to replace the generic memory model in the project altera_emif_ddrx_model.sv model to make it work.
However, for system level simulation (eg, PCIE + EMIF), it is recommend to run the simulation using abstract phy mode as this will save the simulation time.
Rgds
BC