I'm doing a Modelsim simulation with the Arria 10 EMIF DDR4. Using the IP generated testbench. The abstract PHY option is relative fast, using the DDR4 memory model is painfully slow.

Vikas,

By the way, another interesting fact. My Platform design Arria 10 GX project has a PCIe HIP and some external memory connected to the EMIF controller. In Platform Designer, if I generate a system level testbench or just a EMIF example design, the simulation fails with multiple complications that relates to the EMIF interface when not using Abstract Phy. If I generate a EMIF Arria10 controller IP using the IP Catalog from the main Quartus window and generate a example design, the DDR4 simulation passes with or without using the Abstract Phy. So I examined the two generated memory models and found them to be different. As I drill down through the instantiations, the working memory model uses the altera_emif_ddrx_model.sv model. The non-functional memory model drills down to a different module called top_inst_emif_mem_bfm_ip_altera_conduit_bfm_181_tj245tq (for my design) and this file uses many function calls to generate the memory signaling. I'm not going to pursuit this any further since I found a workaround solution, just thought it might be interesting to your readers.

Regards,

George