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Altera_Forum
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16 years ago

IIR in DSP-Builder with modified multiplier LUT or multiplie accumulate

Hi, I want to realize a filter bank with 32 x IIR band-pass filter with reduced Multiplier. I have a Altera DE2 board Ciclone 2, FPGA EP2C35F672C6N, possess only 70 9x9 Multiplier. Can someon...
Altera_Forum's avatar
Altera_Forum
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16 years ago

the filterbank have 32 IIR-bandpassfilter with 32x16 coefficient.

the application is a mp3-encoder/decoder in dsp-builder.

I have resolt my schematic with LUT.

The audio-signal is sampled with 48kHz and the load of coeff in multiplier from LUT with 48kHz x 32 = 1.536MHz. I use Base clock (48kHz) and a derivate clock with 1/32 dimension --> 48kHz / (1/32) = 1.536MHz. But I d'ont can simulate, I have the following errormessage:

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Error reported by S-function 'sGeneric' in audio_path.mdl

Two ports have different clocks clock_1.536MHz and clock_48kHz, where they should have the same

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my e-mail is maranello(at)hispeed.ch, so I can send you my mdl-file...