thepancake
I did consider some type of dc offset going on. However, I don't see this zero position spike in the Verilog sim which is full of truncations. Actually, the Matlab core model sim is designed to truncate values exactly how/where I truncated the Verilog values so that I have exact match between the two. It just looks like a difference between the Verilog simulation model (.vo) and the Matlab core model.
Will crawl thru the two sims again to look for any difference.
I would just ignore it but a spike at the (0,0) point is valid for no shift between the two images which is a possibility.
Thanks for your input.