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ldm_as
Occasional Contributor
6 years agoActually I wanted to see a Verilog/VHDL code, which implements a Slave Avalon-MM interface. This interface should support different latency of transactions (latency 0, 1, ...)
Actually I wanted to see a Verilog/VHDL code, which implements a Slave Avalon-MM interface. This interface should support different latency of transactions (latency 0, 1, ...)