I2C core issue

skaneta,

clock rate iss not a generic; it's programmed into a configuration register -- you configure the division factor.

CosworthRS,

as other have pointed out, you have the SDA and SCL signals wrong.

First, you should take the sda_i, sda_o and sda_oen signals to the FPGA top level. Common practice is not to have internal tri-state signals in FPGA designs.

Secondly, the correct way to handle it is:

sda_i <= SDA;

SDA <= '0' when sda_o = '0' and sda_oen = '0' else 'Z';

Rinse and repeat for SCL.

This will get Quartus to infer an open drain configuration for the SDA and SCL pins.