I using trancseiver native PHY IP core and reset controller for Ethernet 10G in my project. Clock is stability(644.53125MHz).Reset controller in A10/C10 default mode. From FPGA fabric transmitted clock 156.25MHz. Rx_rdy from reset controller at null. Why

HI,

Rx_rdy stuck low typically means the transceiver channel is still stuck in reset stage. Normally caused by issue with clocking, reset or your top level design connection.

To ease your debug, you can leverage below simple example design to bring up the transceiver channel first (out of reset) to help isolate the problem is with your Quartus design, chip or board.

• https://fpgacloud.intel.com/devstore/platform/17.1.1/Pro/cyclone-10-gx-xcvr-toolkit-reference-design/

Thanks.

Regards,

dlim