Hi:
As you see, I indeed encountered some problems, which come from the FPGA chip of 5CGXFC3B7F23C8N. When I use the GXB bank ,CH L1 always compile error.
Here are the answers you established：
1. the Quartus version is 18.0;
2. my board;
3. cv_GX_1ch_40b_3125mbps design example , I download it in “interFPGA ”website “on-chip debugging design examples”;
4. the error is “14566 Could not place 1 periphery component（s） due to conflicts with existing constraints (1 channel PLL(s)”
Hope you can help me . Looking forward to you reply.
Best regards,
Qiushi Wang
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mobile ： 18810644922
email ：
wangqiushi@cgnpc.com.cn
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