JHUAN157
New Contributor
New ContributorForum Discussion
JonWay_altera
Frequent Contributor
Frequent ContributorHi @JHUAN157
In order for me to assist you.
Could you provide more info:
- what version of Quartus are you using
- what machine are you using? Windows/Linux?
- how to replicate
- what debug have you done so far
- have you tested on other machines
- does this happen to other IP or PLL IP only?
- does this happen to vhdl only? or verilog too?
- what are the other debug done?
JHUAN157New Contributor
New ContributorJW,
I am using Quartus II 64-bit Version 13.1.0, Microsoft Windows 10 Pro.
To replicate:
In the Quartus II Window, Tools -> MegaWizard Plug-In Manager
In the MegaWizard Plug-In Manager window [page 1], select “Create a new custom megafunction variation”, and click Next.
In the MegaWizard Plug-In Manager window [page 2], on the left column, click on PLL -> Altera PLL V13.1. On the right column, select VHDL, and put pll.vhd in the output file field. Click on Next
The Altera PLL window pops up. I did not change anything in the Altera PLL window. Everything is default. Click on Finish.
Error occurs. Error: Execution of script C:/Users/JASONH~1/AppData/Local/Temp/alt8116_4978854645064875100.dir/0002_pll_gen/proj.tcl failed
I have not tried other machines. I generated fifo.vhd from the FIFO IP with no errors. It happens to both vhdl and Verilog.
Thanks,
Jason
