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Altera_Forum
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17 years ago

I come across a problem about pll

I use the ep2s60 mini-board.when 50Mhz clock is devided into 25Mhz and 10Mhz,I find that the high level of 25Mhz clock is 1.8 v but 10MHz is 3.3v by oscillograph .Why:confused:? Thank anyone who ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

You can drive a clock out on any general purpose I/O. The PLL clock output pins have dedicated circuitry to provide a low-jitter clock output.

Jake