Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I come across a problem about pll

I use the ep2s60 mini-board.when 50Mhz clock is devided into 25Mhz and 10Mhz,I find that the high level of 25Mhz clock is 1.8 v but 10MHz is 3.3v by oscillograph .Why:confused:? Thank anyone who ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

The PLL and it's output clocks are completely unrelated to voltage levels. Those clocks are generated internal to the chip. Apparently you have chosen to output those clocks on the FPGAs I/O pins (or maybe dedicated clock output pins). In such a case, the output voltage level will correspond to whatever value of VCCIO you have for that I/O bank.

So, your 25Mhz clock is being put out on an I/O bank with 1.8V VCCIO and your 10MHz clock is being put out on an I/O bank with 3.3V VCCIO.