I am trying to incorporate in Quartus II project a IP In-System Sources and Probes with a port size (source / probe) of 512 bits [511..0], but when compiling the following error occurs:

Question

Error (10652): VHDL Assertion Statement at altsource_probe_body.vhd(451): assertion is false - report "SOURCE_WIDTH must be less than and equal to 511 and greater than and equal to 0" (FAILURE or ERROR).

Although the documentation indicates that a 512-bit size port can be created, I can only make them of size 511.

What can be the cause? bug?

richardt_altera · Answer

Hi, may I know which document that you refer to that indicates a 512-bit size port can be created?

vcarr5 · Answer

In Intel® Quartus® Prime StandardEdition Handbook Volume 3 (https://people.ece.cornell.edu/land/courses/ece5760/DE1_SOC/Power_Estimation/qts-qps-5v3.pdf), page 53 say:

"...Especify the desired parameters for your custom IP variation.

You can specify up toup to 512 bits for each source. Your design may include up to 128 instances of thisIP core..."

richardt_altera · Answer

May I know which Quartus version are you using?

vcarr5 · Answer

I am using Quartus Prime version 19.1.0 (build 670 09/22 2019) SJ Lite Edition.I have tried with previous versions under Windows and Linux systems but this problem is still there ..

richardt_altera · Answer

0:511 equates to 512 bits. The count starts from 0. You may see other Quartus version with port width 0:512, engineering confirm that 0:512 is a bug. Correct fix should be 0:511.

Forum Discussion

I am trying to incorporate in Quartus II project a IP In-System Sources and Probes with a port size (source / probe) of 512 bits [511..0], but when compiling the following error occurs:

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