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GRose12's avatar
GRose12
Icon for New Contributor rankNew Contributor
6 years ago

I am trying to create a Viterbi IP block and use in my Arria V GZ design. I am not running an Avalon bus internal. I see that when I choose the Viterbi IP from the DSP/Error Detection and Correction section, it is generated using Qsys.

I have 2 questions: Can I directly connect to this IP and not use an Avalon Bus interface Can I simulate this core in ModelSiim
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

As I understand it, you have some inquiries related to the Viterbi IP in AVGZ devices. Please see my responses to your inquiries as following:

1. Can I directly connect to this IP and not use an Avalon Bus interface

[CP] Yes, you can directly connect this IP in your RTL. Note that the signals at the interface would need to follow the Avalon requirement ie SOP, EOP, Valid and etc.

2. Can I simulate this core in ModelSiim

[CP] Yes, you can generate simulation example design through IP Paramemter Editor -> Generate -> Generate Example Design.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

  • GRose12's avatar
    GRose12
    Icon for New Contributor rankNew Contributor
    6 years ago
    Chee, Thank you for the information. I followed your instructions and I worked with Steve Zack this morning who is a Arrow/Intel FAE for my territory. He helped me understand that I wanted to use the Viterbi IP in Continuous Mode, so I have changed the IP setup. I have built a ModelSim project to try to simulate the IP and I am still having issues. I don’t see in the ug_viterbi-compiler.pdf document exactly how to run in continuous mode. On page 35 and 36 are the only timing diagrams but they are not for continuous mode. I have setup my ModelSim test bench and here is my waveform output showing that the logic flow with decbit, source_val and decbit being undefined. [cid:image003.png@01D5DB78.CBFF1CB0] My first question is will I be able to simulate the Viterbi IP in ModelSim. If so, what files do I need to include. Best regards, Glenn Rosenthal Ulyssix Technologies, Inc. DATT Summit Phone: 301-846-4800 ext. 301 Fax: 301-846-0686 www.ulyssix.com<http://www.ulyssix.com/> www.dattsummit.com<http://www.dattsummit.com/> "Where technology soars" [cid:image004.jpg@01D5BEF7.9952AEF0]<http://www.dattsummit.com/>[cid:image005.png@01D5BEF4.A5AE7830]<http://www.dattsummit.com/floor-plan>