Honored Contributor
Honored ContributorWe had the very same problems and it turned out that it is the same root cause. Thanks for sharing your thoughts and solution with this issue!
Since we cannot wait for the next HW revision, I had to find a simple fix for our stock boards: For the moment I instantiate a second pair of differential clocks on unused pins of the primary bank, which already manages DQ with a proper reference voltage. Next I made these clocks the ‘main’ clocks mem_clk[0]/mem_clk_n[0]. My non-readable clock pins, that are actually connected to the memory devices, are now specified as a second pair mem_clk[1]/mem_clk_n[1] in MegaWizard. In this way, the unconnected pins can be used for calibration tasks, and the connected pins drive the memory. This worked out of the box. I will use a lower clock as I expect the calibration to be less accurate if the pins used for calibration don’t have any load. What puzzles me is that the HPC II memory controller from Quartus II 9.1 SP2 worked without this trick, but from a quick code inspection I would reckon that this version uses the clock pin mem_clk[0] as an input, too. So the question is, why it works in 9.1 but not in 10 onwards. We already considered going back to 9.1 for this very reason, but I feel much more comfortable using this hack on a more recent Quartus release with final Arria II GX support than the old 9.1 with just preliminary timing. Well … HPC II itself still has preliminary support on Arria II GX, but in general we don’t want to trust 9.1 regarding timing.
