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EZuba's avatar
EZuba
Icon for New Contributor rankNew Contributor
7 years ago

How works the ODT signal on LRDIMM DDR4?

Let me explain my problem. Im going to connect Arria10 FPGA with MTA72ASS8G72LZ. In this case, hard phy has only one signal ODT, while memory has two ODT inputs. User guide says that one is ok, but i...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Yes, this is true. You can use one ODT from FPGA connect to 2 ODT on the same DIMM. Using balanced tree topology.

To explain further why we only need one. The reason is because for LRDIMM, the data bus is buffered. So the CS will already disable the other rank data buffer. Even you turn on ODT or not to the other rank, it will not take any effect to data bus.