Forum Discussion
JKastil
New Contributor
New ContributorHow to use DCFIFO for clock crossing?
We are using manual instantiation of the DCFIFO in the SystemVerilog for the clock crossing between two asynchronous clocks (no relation between the clock). Since the write and read clocks are not ...
GuaBin_N_Intel
Contributor
Contributor.... constraints do not work correctly. Was the issue solved?
No for stated device families, you have to add such constraints defined in the KDB.
..Does this mean, that we should not have the read clock and write clock in different clock groups?
Both read and write clock could NOT be constrained in different clock groups. Those transfers between them will be ignored in timing analysis if we doing so and may cause functionality issue.
.....for all dcfifos in the design. Is this correct?
Yes, user have to add those constraints for dcfifo if there is no SDC included and confirm they are valid in timing analysis . Please refer to either KDB or DCFIFO user guide.
