Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHow to test user logic
Hi,everyone, I wrote a user logic to make Nios II read data from a fifo.The ports defination as follow: clk, resetn, //interface to Avalon chip_select, address, write_n, write_data, ...
Altera_ForumHonored Contributor
Honored ContributorYou will need to create a test bench (Ideally in Verilog) to stimulate your design.
http://www.asic-world.com/verilog/art_testbench_writing2.html#writing_a_testbench Has some good pointers as to how to write a testbench. My advice would be start simple but design for flexibility.
