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BXia's avatar
BXia
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

How to set the LVDS SERDES intel FPGA IP for receiving mini-LVDS signal

Hi,

I'm using the LVDS SERDES intel FPGA IP to receive Mini-LVDS signal, I need to receive 2 data by a clock, however, the minimum SERDES factor is 3, so how to set the IP, or anything else I need to set?

Is there a Mini-LVDS example for reference?

Thanks in advance.

2 Replies

  • YuanLi_S_Intel's avatar
    YuanLi_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi, it would be better if you could choose mini-LVDS IO standard in FPGA to interface with mini-LVDS input.


  • YuanLi_S_Intel's avatar
    YuanLi_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you