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Altera_Forum
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13 years ago

How to run gate-level simulation for DDR2 SDRAM Controller

Hi all, I am working with DDR2 SDRAM and I have built a DDR2 SDRAM Controller in Startrix IV (an UniPHY IP) using MegaWizard Plug-In Manager Tool of Quartus 11.1. I have also written a simple t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi jacklsw86,

Thanks for your reply. I found the reason why the gate level simulation behaved uncorrectly. This is the fault of Quartus II. So if we want to verify the timing, we have to use the TimeQuest Timing Analyzer tool.