How to run gate-level simulation for DDR2 SDRAM Controller

Yes, you only need .vo and .sdo files to run gate-level simulation but SDC file affects your implementation (fitter). constraint your clock so that the quartus can fit the design properly. (eg. say you are using 100MHz clock, specify the clock period in .sdc file). run timing analyzer to see whether there are any timing violations (setup or hold error).

most likely your design does not meet timing closure if you said it is working in functional simulation but not in gate-level simulation. try to look for the timequest analyzer tutorials in altera website for more details.