How to run gate-level simulation for DDR2 SDRAM Controller

how can DDR2 controller does not instantiate correctly in gate-level simulation? you said it was ok in RTL simulation, but remember RTL is just functional simulation that does not take care of delays in the hardware. If it worked in RTL but not in gate simulation, you might wanna check your timing constraints in SDC file (or see your timing analyzer if the timing fails)