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Altera_Forum
Honored Contributor
Honored ContributorHow to run gate-level simulation for DDR2 SDRAM Controller
Hi all, I am working with DDR2 SDRAM and I have built a DDR2 SDRAM Controller in Startrix IV (an UniPHY IP) using MegaWizard Plug-In Manager Tool of Quartus 11.1. I have also written a simple t...
Altera_ForumHonored Contributor
Honored Contributorhow can DDR2 controller does not instantiate correctly in gate-level simulation? you said it was ok in RTL simulation, but remember RTL is just functional simulation that does not take care of delays in the hardware. If it worked in RTL but not in gate simulation, you might wanna check your timing constraints in SDC file (or see your timing analyzer if the timing fails)
