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Altera_Forum's avatar
Altera_Forum
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9 years ago

How to "regenerate" an input clock if it's a burst clock

Hi guys, I have a Cyclone IV E and I have an external board which output a 27 Mhz clock with 8 bit data. The board at the end the chain needs to work another couple of signals (valid and sync) ...
Altera_Forum's avatar
Altera_Forum
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9 years ago

It seems that you are working with TS packets.

You can use a FIFO with separate clock ports for read & write.

Use the input 27 MHz clock as write clock and feed the FIFO data port with the same input data.

Design a simple state machine or a sequential code (process for VHDL OR alway block for Verilog) to read from that FIFO with your local 27 MHz clock which is connected to the read clock port.

You can now read from FIFO and issue your valid & sync signals based on output of FIFO which is synchronous with your logic.