Forum Discussion
ContributorHow to manual control the E-Tile transceiver's CDR mode of agilex 7
Hi,
fpga chip : AGFB014R24B2E3VNL
Issue : rx_set_locktodat and rx_set_locktoref doesn't present in E-Tile's Transceiver's CDR, and I didn't found the related avalon register to control this part in the E-Tile Transceiver PHY user guide
Does E-Tile transceiver support this feature in Agilex 7 Device? If so, could you please share this part information?
Best Regards,
Lambert
Hi Lambert,
Yes, your understanding is correct. There is no workaround to control CDR in E-Tile. You may explore Agilex 5 GTS XCVR which support the rx_set_locktoref control. Thank you.
3 Replies
CheepinC_alteraRegular Contributor
Hi Lambert,
Good question — this is a common point of confusion when migrating from L-Tile/H-Tile designs or looking at F-Tile documentation.
**The short answer: `rx_set_locktoref` and `rx_set_locktodata` are not features of the E-Tile transceiver CDR.**
The signals `fgt_rx_set_locktoref` / `rx_is_lockedtoref` you may have seen documented (e.g. in F-Tile PMA/FEC Direct PHY IP user guides) are specific to the F-Tile PMA (FGT/FHT). They are not part of the E-Tile architecture.
Please let me know if there is any inquiry. Thank you.
lambert_yuHi,
Thanks for your response.
Now we have requirement for CDR's working mode for special high speed protocol.
From your information, If we want to control CDR's working mode more precisely, there's no any work around solution, right? That means we need to change to other FPGA chip?
Best Regards,
Lambert
- CheepinC_altera
Hi Lambert,
Yes, your understanding is correct. There is no workaround to control CDR in E-Tile. You may explore Agilex 5 GTS XCVR which support the rx_set_locktoref control. Thank you.
