How to interpret 8b/10b convert in the JESD204b bus

Hello,

1. Observation: From one of 16 bits output signal outxTxSerialData in the JESD204B serial bus, I can figure out that there are 40 bits transitions during one clock (tx_link_clk_clk) cycle, that scenario meant that the input has 32 bit parallel data when JESD204B used 8B/10B encoding technical from your JESD204B datasheet . From your protocol there are up and low 32 bits parallel data transfer to form 64 bits parallel data that matches your AV bus input. As a result, 64 parallel bus coordinate with one bit serial bus in the JESD204B output
2. Confuse: When I pick up one output serial bus, the 10 toggling patterns are 1111101011 following with 0000010100 during half of tx_link_clk_clk clock cycle, which it preforms RD=-1 and RD=+1 patterns generation. Now I review the 8b/10B encoding table, and none of above pattern matches the Wikipedia .
3. Requirement: Can you give me the encoding technical table so I can detect whether input parallel data through JESD204B IP is correct or not? It will be benefit during my system bring up

Thank you so much for your help in advance!

-Fred