Contributor
Regular ContributorHi,
I have concern on the nConfig and CONF_DONE pin.
The nConfig should be released except that something is driving this low. Do you have osciloscope to scope this signal?
The CONF_DONE will only be released to high by FPGA when the configuration is completed. If the nConfig is low then the CONF_DONE shouldn't be high.
ContributorHi @JohnT_Intel
Yes, I am using a logic Analyser scoping nConfig + CONF_DONE & nStatus.
Those readings I supplied were before even autodetecting the flash and loading the application code to check if FPGA is configured. You just asked me for the status of those signals after power cycle & I supplied them to you.
Why did you state that "if the nConfig is low then the CONF_DONE shouldn't be high" at that stage?
Wrt page 1:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cfg/cfg_cf51001.pdf
At the beginning before configuration starts (ref. Fig1) nConfig is low, CONF_DONE is high & nStatus is high so it looks like we are at that stage. I'm I not correct to state this ?
----
I carried on autodetecting the flash & then loading the application code.
In the latest run, I noticed CONF_DONE being low, nStatus being high and nCONFIG low
Configuration somehow kickstarted because noticed DCLK pulsing and CONF_DONE went high at the end of the configuration cycle BUT nConfig was low throughout this time. Application code was not running (ie FPGA configuration not fully working).
So, yes nConfig could be the issue during the Configuration phase. Expected that pin to be high. Please confirm here.
Regards,
Kevin
