How to give sync Pattern for 32 bit or 40 bit wide channel in altera custom phy transceiver ip?

HI,

Pls see my reply below

1. Regarding word aligner block bit width is always < 20 bits support

• This is due to there is another "byte deserializer" block at transceiver RX data path that further deserialized the data width (x 2). Output from "byte deserializer" block will always be 2 byte of data packet running in half of previous operating frequency
  • word aligner (20 bits) -> byte deserializer (40 bits) -> FPGA core logic
  • You can read more about transceiver PCS block architecture in below user guide (chapter 1, page 43)
  • https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-v/stx5_xcvr.pdf

1. Regarding word aligner "rx_syncstatus" port support

• From custom phy IP, I can see that rx_syncstatus can be enabled in both "manual mode" and "auto mode" but not bitslip mode

1. In general, you can refer to below user guide chapter 10 - custom phy IP core (page 252 onwards) to learn more about the IP feature and usage guideline

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/xcvr_user_guide.pdf

Thanks.

Regards,

dlim