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matif's avatar
matif
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

How to give sync Pattern for 32 bit or 40 bit wide channel in altera custom phy transceiver ip?

​Hi, in altera transceiver custom phy ip, I selected channel length to be 40 bit. Now in syncpattern option, what value do I enter? I usually enter h'BC when my channel width is 8 bit or 16 bit?

3 Replies

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    The sync pattern requirement typically follow IP protocol requirement. For instance, your BC pattern is derived Ethernet K28.5 data pattern.

    So, it's either you follow the protocol requirement or you are free to define your own data pattern as well.

    In Custom PHY Intel FPGA IP, you can configure below parameter

    • pattern length : either 8, 16 or 32 bits
    • pattern value : to be any value or follow certain protocol requirement

    Thanks.

    Regards,

    dlim

    • matif's avatar
      matif
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      ​Hi, thanks a lot for your reply. Just wanted to ask one more thing. The word allignment mode of automatic synchronization state machine and bit sllipping only works with 8 or 16 bits but I wana work with 40 bits transceiver channel. The thing is that I wana use rx_syncstatus port which I think works only if I have word allignment mode of automatic synchroniztion statemanchine or bit slipping is selected? There is another option of manual. What is that? Will rx_syncstatus still work if I select manual option?

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    HI,

    Pls see my reply below

    1. Regarding word aligner block bit width is always < 20 bits support
    • This is due to there is another "byte deserializer" block at transceiver RX data path that further deserialized the data width (x 2). Output from "byte deserializer" block will always be 2 byte of data packet running in half of previous operating frequency
    1. Regarding word aligner "rx_syncstatus" port support
    • From custom phy IP, I can see that rx_syncstatus can be enabled in both "manual mode" and "auto mode" but not bitslip mode
    1. In general, you can refer to below user guide chapter 10 - custom phy IP core (page 252 onwards) to learn more about the IP feature and usage guideline

    Thanks.

    Regards,

    dlim