Altera_ForumHonored Contributor14 years agoHow to get the FIFO informations hi all , recently i modify the reference design "a2gx125_qsys_pcie_gen1x4_11_0_1"(using a dual clock onchip_fifo_memory replace the original onchip_memory,BTW,thanks to the author of this reference d...Show More
Recent DiscussionsF-Tile xcvr placement on DK-DEV-AGF023FAMAX10 TSE reference designCyclone-V SCFIFO with M10K/MLAB memory - adding ECCConstraints not being picked for DCFIFOCyclone 10 GX IBIS-AMI models