alexislms
Contributor
3 years agoHow to get the DCFIFO constraints right for once and for all?
I'm used to the Xilinx XPM libraries, they automatically add all the necessary constraints.
I'm trying to use DCFIFO but I really struggle.
First, I read embedded constraints are automatically added when dcfifo is used.
- https://www.intel.com/content/www/us/en/docs/programmable/683522/18-0/embedded-timing-constraint.html shows my instances
- shows the instances HAVE to contain dcfifo...
- Why aren't they scoped to all dcfifo's instances regardless of their name?
I then renamed all my instances with dcfifo.
A compilation later, I still see lots of CDC timings, among others:
FIFO_CMD.cmd_dcfifo_i|auto_generated|delayed_wrptr_g[5]~DUPLICATE FIFO_CMD.cmd_dcfifo_i|auto_generated|rdemp_eq_comp_msb_aeb FIFO_CMD.cmd_dcfifo_i|auto_generated|delayed_wrptr_g[3]~DUPLICATE FIFO_CMD.cmd_dcfifo_i|auto_generated|rdemp_eq_comp_msb_aeb FIFO_CMD.cmd_dcfifo_i|auto_generated|delayed_wrptr_g[5] FIFO_CMD.cmd_dcfifo_i|auto_generated|rdemp_eq_comp_msb_aeb~RTM_6
Why do I get these timings? Why aren't they automatically constrained?
I also get CDC timings on the reset paths even though I set both parameters read_aclr_synch and write_aclr_synch to "ON" and the reset is synchronous to the write clock. I've also tried read_aclk_synch=OFF and write_aclk_synch=ON.
dcfifo #( .intended_device_family ("Agilex"), .lpm_numwords (512), .lpm_showahead ("ON"), .lpm_type ( "dcfifo"), .lpm_width (576), .lpm_widthu (10), .add_usedw_msb_bit ("ON"), .read_aclr_synch ("ON"), .write_aclr_synch ("ON"), .rdsync_delaypipe (2), .wrsync_delaypipe (2) ) usr_dcfifo_i ( .aclr (s_app_reset), .wrclk (s_app_clk), .wrfull (usr_fifo.wr_full), .wrreq (usr_fifo.wr_en), .data (usr_fifo.wr_data), .wrusedw (usr_fifo.wr_data_count), .rdclk (m_axi_clk), .rdempty (usr_fifo.rd_empty), .rdreq (usr_fifo.rd_en), .q (usr_fifo.rd_data), .rdusedw (usr_fifo.rd_data_count), .eccstatus (), .rdfull (), .wrempty () );
Regards,