Contributor
Super ContributorHi Alexis,
According to DCFIFO Timing Constraint Setting in the link below, FIFO parameter editor provides the timing constraint setting for the DCFIFO function. A user configurable SDC file is generated automatically when DCFIFO is instantiated from the IP Catalog. New timing constraints consist of set_net_delay, set_max_skew, set_min_delay and set_max_delay are used to constraint the design properly.
ContributorHi,
I don't use the IP Catalog and I don't generate an IP, I directly use the primitive dcfifo as shown in the OP.
We would like to avoid having to create/generate an IP for a simple fifo, unnecessary extra dependencies are unwelcome.
Also, even by using a "FIFO Intel FPGA IP", disabling "Generate SDC file and disable embedded timing constraint" gives the same timing errors.
My question is regarding the DCFIFO's embedded constraints. Some constraints are missing.
Regards,
