Forum Discussion
Nagaraju
New Contributor
New ContributorHow to generate MSIx interrupts in AvalonMM Startix10 PCIe HardIP+ when configured it as end point. And there are no signals like tl_cfg_ctl,tl_cfg_add,tl_cfg_func,MSIx_intfc_o which are available in other PCIe IPs of startix 10 why?
SengKok_L_Intel
Regular Contributor
Regular ContributorHi,
For AVMM Stratix 10 PCIe Hard IP+, the MSI/MSI-X interface needs access via tl_cfg, but this interface is now not available at the top level. However, you can still find this interface at a lower layer instance which is "intel_pcie_s10_avmm_bridge_512.sv". I will feedback this to the Intel PSG engineering team to export those signals to the top level so that the user can access it directly without any manual modification.
Regards -SK
- SengKok_L_Intel
Just for your information, the Intel PSG engineering team is in progress to enhance the IP to address this concern in the future IP release.
Regards -SK
NagarajuNot on Avalon MM Interface, how I can read the MSIx Capability registers and TPH capability Registers. Beacuse they need to be used in my RTL.
