how to efficiently drive async SRAM?

You might be able to do something similar to what (appears to) happen on the nios cpu's tightly coupled data memory.

Reads are done every clock, with the read data being available a clock after the address. This happens whether or not the instruction opcode is a 'ldxxx' never mind which memory block is actually selected.

A write can only be done after the address decode has happened, so the address for writes is only availabe a clock later than that used for reads. Writes can still happen every clock.

If a read follows a write (to the same memory block) then the read has to stall for one cycle - since the memory block was presented with the wrong address.